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| SSM6679M P-CHANNEL ENHANCEMENT-MODE POWER MOSFET Simple drive requirement Low on-resistance Fast switching characteristics D D D D BVDSS RDS(ON) G -30V 9m -14A ID SO-8 S S S Description Advanced power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is widely preferred for commercial and industrial surface-mount applications and is well suited for low voltage applications such as DC/DC converters. D G S Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating -30 25 -14 -8.9 -50 2.5 0.02 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 50 Unit C/W Rev.2.02 4/06/2004 www.SiliconStandard.com 1 of 4 SSM6679M Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA 2 Min. -30 -1 - Typ. -0.03 26 37 3 25 13 11 58 43 950 640 Max. Units 9 13 -3 -1 -25 100 60 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA Static Drain-Source On-Resistance VGS=-10V, ID=-14A VGS=-4.5V, ID=-11A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=-250uA VDS=-10V, ID=-14A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS= 25V ID=-14A VDS=-24V VGS=-4.5V VDS=-15V ID=-1A RG=3.3 ,VGS=-10V RD=15 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 2860 4580 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=-2A, VGS=0V IS=-14A, VGS=0V, dI/dt=100A/s Min. - Typ. 48 46 Max. Units -1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 125 C/W when mounted on Min. copper pad. Rev.2.02 4/06/2004 www.SiliconStandard.com 2 of 4 SSM6679M 280 150 240 T A = 25 C o -10V -7.0V -ID , Drain Current (A) T A = 150 o C -10V -7.0V -5.0V -4.5V -ID , Drain Current (A) 200 100 160 -5.0V -4.5V 120 50 80 V G = -3.0 V V G = -3.0 V 40 0 0 1 2 3 4 5 0 0 1 2 3 4 5 6 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 14 1.8 I D = -11 A T A =25 12 1.6 I D = -14 A V G =-10V Normalized R DS(ON) 3 5 7 9 11 1.4 RDS(ON) (m) 10 1.2 1.0 8 0.8 6 0.6 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 14 12 10 2 8 6 T j =150 o C T j =25 o C -VGS(th) (V) 1 0 -50 -IS(A) 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Rev.2.02 4/06/2004 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 4 SSM6679M f=1.0MHz 12 10000 -VGS , Gate to Source Voltage (V) 10 I D = - 14 A V DS = -24V Ciss 8 C (pF) 6 1000 Coss Crss 4 2 0 0 20 40 60 80 100 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 9. Gate Charge Characteristics 100 Fig 10. Typical Capacitance Characteristics 1 1ms 10 Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 0.1 0.1 10ms -ID (A) 1 0.05 100ms 1s 0.02 PDM 0.01 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125oC/W 0.1 T A =25 C Single Pulse 0.01 o DC 0.001 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area VDS 90% Fig 8. Effective Transient Thermal Impedance VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.02 4/06/2004 www.SiliconStandard.com 4 of 4 |
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